1. Field of the Invention
The present invention relates generally to memory modules, and more particularly, to a memory module having registers mounted with minimized area and with preservation of signal integrity.
2. Description of the Related Art
A memory module includes registers that receive signals from external devices and transfer such signals to memory chips mounted in the memory module. If the number of memory chips in a memory module is large, the memory module typically includes a plurality of registers.
A number of output pins of each of the registers for connecting to memory chips decreases with higher number of registers for improved signal integrity. On the other hand, a larger area is required for mounting a higher number of registers in the memory module. Also, since a memory controller must transmit signals to each of the registers, a higher number of registers increases the load of the memory controller thus limiting signal integrity.
FIG. 1 illustrates a conventional memory module with two registers. FIG. 2 is a signal connection diagram of the memory module of FIG. 1.
Referring to FIG. 1, a first register RF is mounted on a front surface RANK0 of a memory module 100, and a second register RR is mounted on a back surface RANK1 of the memory module 100. The first and second registers RF and RR are each a 1:2 register that buffers one input signal and outputs two signals equivalent to the input signal.
One 1:2 register can be substituted for two 1:1 registers thereby reducing mounting space and cost. However, the number of input/output pins of the 1:2 registers RF and RR is larger than that of a 1:1 register. Therefore, because of pins, the first and second registers RF and RR are not mounted in the same location on the front surface and the back surface RANK0 and RANK1 of the memory module 100. In other words, the first and second registers RF and RR are not mounted with any overlap between such registers RF and RR.
If a signal INS transmitted to the memory module 100 is an n-bit signal, the n-bit signal is transferred to each of the first and second registers RF and RR. The first register RF simultaneously transfers the signal INS to each of memory banks MLD0 and MLU0 disposed on the front surface RANK0 of the memory module 100 and to each of memory banks MLD1 and MLU1 disposed on the back surface RANK1 of the memory module 100.
Note that each of notations MLD0, MLU0, MLD1, and MLU1 refers to a bank (i.e., herein simply meaning a group) of at least one memory chip. In addition, the memory banks MLD0, MLU0, MLD1, and MLU1 are disposed toward the left side of the first register RF in the memory module 100.
The second register RR simultaneously transfers the signal INS to each of memory banks MRD0 and MRU0 disposed on the front surface RANK0 of the memory module 100 and to each of memory banks MRD1 and MRU1 disposed on the back surface RANK1 of the memory module 100.
Note that each of notations MRD0, MRU0, MRD1, and MRU1 refers to a bank (i.e., herein simply meaning a group) of at least one memory chip. In addition, the memory banks MRD0, MRU0, MRD1, and MRU1 are disposed toward the right side of the second register RR in the memory module 100.
The signal INS includes rank control signals (not shown), which enable ranks of the memory module 100. The rank control signals are transferred only to corresponding ranks.
The front surface RANK0 and the back surface RANK1 of the memory module 100 form a first rank and a second rank, respectively. Therefore, the rank control signal that enables the first rank of the memory module 100 is transferred to the memory banks MLD0 and MLU0 on the front surface RANK0 of the memory module 100 via the first register RF and to the memory banks MRD0 and MRU0 on the front surface RANK0 of the memory module 100 via the second register RR.
The rank control signal that enables the second rank of the memory module 100 is transferred to the memory banks MLD1 and MLU1 on the back surface RANK1 of the memory module 100 via the first register RF and to the memory banks MRD1 and MRU1 on the back surface RANK1 of the memory module 100 via the second register RR.
Because of the number of pins of the registers RF and RR, such registers RF and RR are not mounted in the same location on the front and back surfaces RANK0 and RANK1 of the memory module 100. Thus, the registers RF and RR are not mounted with overlap and are typically mounted side by side on the front and back surfaces RANK0 and RANK1 of the memory module 100, as illustrate in FIG. 1. Therefore, the area used for mounting the two 1:2 registers RF and RR is larger than the area used for mounting four 1:1 registers that may be mounted with overlap between two 1:1 registers on the front and back surfaces of the memory module.
Also, as the number of pins of the first and second registers RF and RR increases, wiring of the pins becomes more difficult, and additional space for the wiring is required. Therefore, in the memory module of FIG. 1, an advantage obtained by using the 1:2 registers is not great.
FIG. 3 illustrates a conventional memory module with four registers. FIG. 4 is a signal connection diagram of the memory module of FIG. 3.
Referring to FIGS. 3 and 4, a memory module 300 includes four 1:2 registers RF1, RR1, RF2, and RR2, each having less input/output pins than each of the first and second registers RF and RR of FIGS. 1 and 2.
Because the registers RF1, RR1, RF2, and RR2 have less input/output pins, the two registers RF1 and RR1 of a first pair are mounted back-to-back for complete overlap, and the two registers RF2 and RR2 of a second pair are mounted back-to-back for complete overlap.
In order to maintain a load of an input signal INS transferred from a controller 410 to the registers RF1, RR1, RF2, and RR2, the input signal INS is divided before being received by the registers RF1, RR1, RF2, and RR2.
For example, if the input signal INS is an n-bit signal, an m-bit signal is transferred to each of the registers RF1 and RF2 on the front surface RANK0, and an (n-m)-bit signal INS is transferred to each of the registers RR1 and RR2 on the back surface RANK1. Thus, the load of the input signal INS transferred from the controller 410 to the registers RF1, RR1, RF2, and RR2 is not increased.
The m-bit signal transferred to the register RF1 on the front surface RANK0 of the memory module 300 and the (n-m)-bit signal transferred to the register RR1 on the back surface RANK1 of the memory module 300 are simultaneously transferred to each of memory banks MLD0, MLU0, MLD1 and MLU1 that are disposed toward a left side of the registers RF1 and RR1. Therefore, each memory chip within the memory banks MLD0, MLU0, MLD1 and MLU1 receives the n-bit input signal INS.
The m-bit signal transferred to the register RF2 on the front surface RANK0 of the memory module 300 and the (n-m)-bit signal transferred to the register RR2 on the back surface RANK1 of the memory module 300 are simultaneously transferred to each of memory banks MRD0, MRU0, MRD1 and MRU1 that are disposed toward a right side of the registers RF2 and RR2. Therefore, each memory chip within the memory banks MRD0, MRU0, MRD1 and MRU1 receives the n-bit input signal INS.
The input signal INS includes rank control signals (not shown), which enable ranks of the memory module 300. The rank control signals are transferred only to corresponding ranks.
The front surface RANK0 and the back surface RANK1 of the memory module 300 form a first rank and a second rank, respectively. Therefore, the rank control signal that enables the first rank of the memory module 300 is transferred to the memory banks MLD0 and MLU0 on the front surface RANK0 of the memory module 300 via the register RF1 and to the memory banks MRD0 and MRU0 on the front surface RANK0 of the memory module 300 via the register RF2.
The rank control signal that enables the second rank of the memory module 300 is transferred to the memory banks MLD1 and MLU1 on the back surface RANK1 of the memory module 300 via the register RR1 and to the memory banks MRD1 and MRU1 on the back surface RANK1 of the memory module 300 via the register RR2.
The conventional memory modules 100 and 300 have similar signal integrity, but the memory module 300 using the four smaller registers RF1, RR1, RF2, and RR2 have smaller register-mounting area.
Nevertheless, the input signal INS transferred from the controllers 210 or 410 of the conventional memory modules 100 and 300 are diverged with a “T” shape. Unfortunately, signal integrity is diminished from impedance mismatching with such T-shaped divergence of the input signal INS.
Also, even though register mounting area of the memory module 300 is less than that of the memory module 100, space is still required for wiring the first pair of registers RF1 and RR1 to any memory bank disposed toward the left of the registers RF1 and RR1 and for wiring the second pair of registers RF2 and RR2 to any memory bank disposed toward the right of the registers.